![]() CPUID.(EAX=07H,ECX=0):EDX enumerates support for indirect branch restricted speculation (IBRS) and the indirect branch predictor barrier (IBPB).Processors that set bit 0 (FORCE_ABORT_RTM) in the IA32_TSX_FORCE_ABORT MSR enable FORCE_ABORT_RTM mode. CPUID.(EAX=07H, ECX=0).EDX and CPUID.(EAX=7H,ECX=0).EDX enumerate support for an updated definition of the IA32_TSX_FORCE_ABORT MSR.CPUID.(EAX=07H,ECX=0):EDX enumerates support for additional functionality that will flush microarchitectural structures as listed here.CPUID.(EAX=07H,ECX=0):EDX enumerates support for the IA32_MCU_OPT_CTRL MSR. The presence of this MSR and RNGDS_MITG_DIS (bit 0) is part of the mitigation for Special Register Buffer Data Sampling.The CPUID instruction enumerates support for the mitigation mechanisms using feature flags in CPUID.(EAX=7H,ECX=0):EDX: To find the mapping between a processor's CPUID and its Family/Model number, refer to the IntelĀ® 64 and IA-32 Architectures Software Developer Manuals, Vol 2A, table 3-8 and the INPUT EAX = 01H: Returns Model, Family, Stepping Information section. ![]() Processor support for the new mitigation mechanisms is enumerated using the CPUID instruction and several architectural model specific registers (MSRs). Refer to the Consolidated Affected Processors by CPU table for a list of processors affected by speculative execution side channels and related security issues disclosed since 2018. Processors Affected by Speculative Execution Side Channel Issues
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